This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-127950, filed Apr. 27, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a nonvolatile semiconductor memory having one page buffer arranged in one column and connected to one bit line and a sense amplifier for a data read.
As nonvolatile semiconductor memories capable of high-speed random access, an EEPROM, NOR cell flash memory, and the like are known. In recent years, in addition to these memories, memories of a new type based on a NAND cell flash memory have been devised. One of such memories is a so-called xe2x80x9c3Tr-NANDxe2x80x9d.
The 3Tr-NAND has been developed as a memory or memory-embedded ASIC to be assembled in a low-power portable device such as a non-contact IC card. One cell unit is constructed by three transistors, i.e., one memory cell and two select transistors which sandwich the memory cell.
A 3Tr-NAND has the following characteristic features, as compared to an EEPROM or flash memory.
(1) A high-speed data read, in units of 16 bits (=one word) is possible.
(2) A data erase can be executed in units of 32 words.
(3) Power consumption in the data read is low.
(4) The memory cell size is small.
More specifically, for example, the 3Tr-NAND has a smaller memory cell size than that of an EEPROM, so the chip size and manufacturing cost can be reduced. The 3Tr-NAND has lower power consumption and a smaller erase unit than those of a NOR cell flash memory.
Since the 3Tr-NAND has been developed based on a NAND cell flash memory, it has a page buffer for temporarily storing program data or read data. One page buffer is provided in correspondence with, e.g., one or a plurality of columns (bit lines).
In addition, the 3Tr-NAND has a sense amplifier for a data read because it is important to execute a data read at a high speed, unlike a NAND cell flash memory that mainly aims at ensuring a large memory capacity.
The sense amplifier has the same structure as that of a sense amplifier used in, e.g., a NOR cell flash memory. For example, the sense amplifier compares a current flowing to a reference cell with a current flowing to a selected memory cell, thereby determining data (xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d) of the memory cell.
Normally, sense amplifiers fewer than columns are arranged in a memory chip because the size of a sense amplifier is relatively large. In the data read, only a column selected by a column decoder is electrically connected to the sense amplifier through a column gate.
In the 3Tr-NAND, a data rewrite (change) is achieved by {circle around (1)} load of program data to the page buffer, {circle around (2)} data erase (xe2x80x9c1xe2x80x9d state is set) for a selected memory cell, or {circle around (3)} data programming (xe2x80x9c0xe2x80x9d-programming or xe2x80x9c1xe2x80x9d-programming) for a selected memory cell, as in a NAND cell flash memory.
In data programming, a program verify is performed to verify whether predetermined data has been correctly programmed in a selected memory cell. The program verify is constituted by a verify read for reading data from a selected memory cell (memory cell in which data is to be programmed) and determining the data value, and detection operation for detecting whether the data read in the verify read matches program data.
In the verify read of a NAND cell flash memory, a page buffer (latch circuit) detects (senses) data from a selected memory cell and determines the data value. In the verify read of a 3Tr-NAND as well, a page buffer can detect data from a selected memory cell and determine the data value.
However, as described above, in the 3Tr-NAND, in the normal data read, read data is detected and its data value is determined by a sense amplifier to realize a high-speed data read. If data value determination in the verify read is done by a page buffer, different data value determination circuits are used for the normal data read and the verify read.
The sense amplifier and page buffer use different levels (threshold voltages) as a determination criterion for xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. For this reason, in the 3Tr-NAND, if the data value determination in the verify read is done by the page buffer, the data value cannot be correctly determined. As a result, for example, even when programming is non-sufficient, it may be erroneously determined that programming is sufficient.
In addition to the above-described 3Tr-NAND, as a nonvolatile semiconductor memory having a page buffer and sense amplifier, a nonvolatile semiconductor memory is disclosed in, e.g., Shin-ichi Kobayashi et al., xe2x80x9cA 3.3 V-only 16 Mb DINOR Flash Memoryxe2x80x9d IEEE International Solid-State Circuits Conference. SESSION7/FLASH MEMORY/PAPER TA 7.2, pp. 122-123, Feb. 16, 1995.
Even in the nonvolatile semiconductor memory disclosed in this reference, read data detection and data value determination in the normal data read are done by a sense amplifier, and read data detection and data value determination in the verify read are done by a page buffer. For this reason, the data value cannot be correctly determined in the verify read.
The present invention has been made to solve the above problem, and has as its object to correctly determine data (memory cell state) in the verify read in a nonvolatile semiconductor memory having a page buffer and sense amplifier.
(1) A nonvolatile semiconductor memory of the present invention comprises a memory cell, a bit line connected to the memory cell, a page buffer connected to one terminal of the bit line to latch data, a read circuit including a sense amplifier for detecting first read data read from the bit line in a normal data read, and a column gate connected between the page buffer and the sense amplifier, wherein in a verify read, second data read out from the memory cell is detected by the sense amplifier.
(2) A verify method of a nonvolatile semiconductor memory of the present invention comprises the steps of, when one page is formed from N (N is a natural number of not less than 2) groups, sequentially selecting the N groups one by one in accordance with a column address Col.Add.=1 to N, continuously performing a verify read and verify data-in for one group selected in accordance with the column address Col.Add.=i (i is one of 1 to N), and continuously performing the verify read and verify data-in for one group selected in accordance with the final column address Col.Add.=N, and then, detecting for all the N groups of one page whether programming is completed (batch detection).
In the verify read, data read out from a memory cell is detected by a sense amplifier in a read circuit, and in the verify data-in, the data is transferred from the read circuit to a page buffer.
(3) A nonvolatile semiconductor memory of the present invention comprises a memory cell, a bit line for transmitting/receiving data to/from the memory cell, and a page buffer connected to the bit line to latch the data. The page buffer comprises a latch circuit formed from first and second inverters which are flip-flop-connected, a first transistor connected between a write circuit and a first node of the latch circuit to input data in a data load, and a second transistor connected between ground and a second node of the latch circuit and having a gate to which data read out from the memory cell in a verify read is input. An input node of the first inverter is connected to the first node, an output node of the first inverter is connected to the second node, and a third transistor is connected between the first inverter and a power supply terminal, the third transistor being turned off when the data is input to the page buffer. An input node of the second inverter is connected to the second node, an output node of the second inverter is connected to the first node, and a fourth transistor normally in an ON state is connected between the second inverter and the power supply terminal.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.